CV of Yayue Hou

Research Interests

Algorithms and Hardware co-design for machine learning systems.
Compute-in-Memory, including algorithm improvement and hardware efficiency enhancement.
Noise resilient analog foundation models with new model architecture and training techniques.

ASPLOS’25, Zehao Fan, Yunzhen Liu, Garrett Gagnon, Zhenyu Liu, Yayue Hou, Hadjer Benmeziane, Kaoutar El Maghraoui, Liu Liu. “STARC: Selective Token Access with Remapping and Clustering for Efficient LLM Decoding on PIM Systems.” In upcoming 2025 International Conference on Architectural Support for Programming Languages and Operating Systems.
Arxiv’2025, Zehao Fan, Zhenyu Liu, Yunzhen Liu, Yayue Hou, Hadjer Benmeziane, Kaoutar El Maghraoui, Liu Liu. “Context-Aware Mixture-of-Experts Inference on CXL-Enabled GPU-NDP Systems.”
Arxiv’2025, Zhenyu Liu, Yunzhen Liu, Zehao Fan, Garrett Gagnon, Yayue Hou, Nan Wu, Yangwook Kang, Liu Liu. “Bandwidth-Efficient Adaptive Mixture-of-Experts via Low-Rank Compensation.”
ICCAD’25, Yayue Hou, Zhenyu Liu, Garrett Gagnon, Hsinyu Tsai, Kaoutar El Maghraoui, Geoffrey W. Burr, Liu Liu. “SAGE: Saliency-Aware Grouping for Efficient Mapping of LLMs on Analog Compute-in-Memory.” In Proceedings of International Conference on Computer-Aided Design, 2025.
DATE’25, Yayue Hou, Hsinyu Tsai, Kaoutar El Maghraoui, Tayfun Gokmen, Geoffrey W. Burr, Liu Liu. “NORA: Noise-Optimized Rescaling of LLMs on Analog Compute-in-Memory Accelerators.” In Proceedings of Design, Automation and Test in Europe Conference, 2025.

2023-present, Rensselaer Polytechnic Institute, NY. Ph.D. student in Electrical Engineering.
2019-2023, Tongji University, Shanghai. B.Eng. in Microelectronics Science and Engineering.

Programming: Python, Verilog, C/C++, CUDA.
Tools & Frameworks: PyTorch, Anaconda, Huggingface, AIHWKIT (Analog CIM), CACTI, Synopsys, Cadence, LaTeX.
Familiar areas: In-Memory-Computing, Sparsity, Quantization, Parameter-Efficient Fine-Tuning, Hardware-Software Co-design.